Digital communications often require timing and data information to be extracted from an incoming distorted stream. Delays between the timing and the data recovery can be caused by many factors, in particular differences in equalization between the two paths, as well as differences in routing, loading and clock distribution.
A simple method to remove this time skew is desirable. As shown in FIG. 1, the delay through the timing recovery, tt, may not produce an optimum sampling clock, relative to the delay through the data recovery, td. The difference between the two could vary according to the setting of the equalizers, the manufacturing variations in the circuits and the environmental conditions.
Timing offsets between the timing recovery and the data recovery paths result in reduced system performance.
It is, therefore, desirable to provide a method and apparatus that reduces or removes time skew between two paths.